A NEW AES ARCHITECTURE USING DYNAMIC KEY FOR HIGH SECURITY, LOW POWER AND HIGH-SPEED APPLICATIONS

Abstract

Advanced Encryption Standard (AES) is the most secured encryption algorithm. It is a block cipher[1] of 128-bit size and key sizes varying from 128,256, and 512 bits. Based on the key sizes, 128, 256, and 512 bit it has 10, 12, and 14 rounds respectively. The stages in AES are add round key, sub byte, shift row, and mix column. As AES being symmetric, the security of the key is questionable and it even consumes highpower.

The proposed work is based on creating a dynamic key [11] based on the sequence of the blocks of data. Each block is considered a frame of 16 bytes and sent in a sequential manner. Based on the sequence, the dynamic key is generated by incrementing the 16 bytes of the key by one unit. The individual data frame associated with a key is passed through the AESalgorithm, which generates the Cipher Text and to the receiver.The receiver, based on the order in which the encrypted data is received, will find the key to decrypt thedata.As the number of frames increases, the security will be high because the probability of finding the key will be least. The conventional s-box is replaced with a one-dimensional s-box [7] provides low power and high speed.

Simulations and synthesis are done in Xilinx ISE 14.7 version and coding are done in Verilog HDL and the results are obtained on the Xilinx Virtex6 FPGA board.

Keywords: Advanced Encryption Standard (AES), Cryptography, DES and Symmetric Key Algorithms.