In this paper, we have implemented MAC Unit using fast binary counter based on symmetric stacking. Using the Proposed counters in existing stacking-counter-based Wallace tree multiplier architectures MAC has been implemented. The present Wallace multiplier uses full adders and half adders functioning as counters, these counter circuits use chains of exor gates on critical path which results in more delay. To reduce the delay and increase speed of the Counter Based Wallace (CBW) multiplier, full adders and half adders in counter circuits are replaced with symmetric stacking. It results in an efficient area and delay values when compared to conventional Wallace tree based MAC unit.
Keywords: Symmetric stacking, counter, Wallace multiplier, MAC, Verilog