FIR filter is helpful in several applications such as modern signal processing and communication systems. In this paper a optimized FIR filter designed by using radix-4 multiplier based mostly on parallel prefix adder is proposed. This suggested radix-4 multiplier designed with brentkung adder. The parallel prefix adders provides the less insertion delay, this results in increase within the high performance for the calculation within the less time. . The planned radix-4 multiplier is compared with a typical vedic multiplier reduced critical path delay by V-day. This proposed multiplier improves the performance of the FIR filter. This Paper has been implemented in Xilinx ISE version 14.7.
Keywords: Residue Number System (RNS); Reversible Circuits; Modular Adder; Parallel-Prefix Adder.