The ever increasing applications of integrated circuits in the day-to-day useful electronic gadgets are the driving force for the development of low power designs of configurable hardware designs. High speed and low power are the main parameters that are targeted by modern circuit designers.. Multipliers are the very important logic operational unit of any processing unit in digital signal processing applications. The speed and performance of multiplier is among the efficiency improvement parameters of any digital hardware design. Another important feature of hardware designs is self-testing ability. This feature provides reliability to the hardware mainly in case of configurable hardware applications.
BIST based approach is used for the implementation of a multiplier using a configurable hardware. A 4-bit low power multiplier design is used as a test logic design. The multiplier design is implemented using gate level architecture representation for realizing the low-power hardware. A gate level combination is used to generate a half-adder and a full-adder design. These adder design block are used in combination to generate the multiplier using the adder terms.
For the BIST implementation, a test pattern generator with random output value is required. For TPG realization, a low-power modified design of linear-feedback-shift-register (LFSR) is used in this design implementation. A 3-register is used for the generation of a 4-bit random number. It is a comparative low power design realization as compared to other existing test power generator designs. Most of the existing TPG have a register-to-bit ratio of ‘1’. In this project, the TPG has a register-to-bit ration of 3:4. This circuit generates a 4-bit random value using only 3-registers, so relative low power consumption is caused by this circuit. In this project, using this BIST technique various multipliers are implemented and compared.
Keywords: Built-In-Self-Test, Test Pattern Generator, Linear Feedback Shift Register, Xilinx.