On-chip communication architectures play an important role in determining the overall performance of System-on- Chip (SoC) designs. Communication architectures should be flexible so as to offer high performance over a wide range of traffic characteristics. In state-of-the-art multi-processor systems-on-chip (MPSoC), interconnect of processing elements has a major impact on the system’s overall average -case and worst-case performance. In shared SoC bus systems, arbiters are usually adopted to solve bus contentions with various kinds of arbitration algorithms.
In shared-memory MPSoCs buses are still the prevalent means of on-chip communication for small to medium size chip-multiprocessors (CMPs). Still, bus arbitration schemes employed in current architectures either deliver good average-case performance (maximize bus utilization) or enable tight bounding of worst-case-execution time. This paper presents a shared bus arbitration approach allowing high bus utilization while guaranteeing a fixed bandwidth per time frame to each master. Thus it provides high-performance to both real time and anytime applications or even a mixture of both.
Keywords: On-Chip Bus, Arbiter, MPSoC.