The requirements of digital circuitries with high speed are highly desirable as portable multimedia & communication applications incorporated with computations & information processing. The disadvantages in the computers degradation of arithmetic functions like addition, subtraction, division & multiplication over the factors of higher consumption of power, carry propagation time delay & bigger circuit complexities. This system identifies carry free n digits addition/subtraction where carry propagation delay is an important factor related to speed of a digital system. In this thesis, QSD numbers are those having radix 4 that is applied in arithmetic functions for executing carry free arithmetic operations. The QSD numbers lie in the range of -3 to +3. Every number from n digit QSD number is presented from a set of -3, -2, -1, 0, 1, 2, 3. In this research, we are working over enhancing performance of QSD addition through implementation of reversible logic gate. QSD addition is implemented for 4 bit & 8 bit. In standard situations QSD adder produces higher delay performance. We need to minimize the delay of 4 bit from 8 bit QSD adder. Peres reversible logic gate & pipelining techniques are applied for minimizing the delay.
Keywords: Carry free addition, Fast computing, FPGA, Quaternary Signed Digit, VHDL, VLSI.