ISSN: 2456-043X

International Journal of Engineering Science and Generic Research

An International Peer Review Journal for Engineering Science and Generic Research

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FPGA Implementation of 16 bit MUX Based Multiplier

Jaganmohan, K.Rambabu

Volume : VOLUME 2 || Issue : ISSUE 5

Abstract :

In digital filter implementation, the multiplier usage is avoided by using MUX based multiplier and Look up Table (LUT) based multiplier. Odd multiple storage proposed by stores the product of odd multiple of co-efficient and the input. The advantage of storing odd multiple is that even multiples can be obtained by a simple left shift operation.8 bit MUX based multiplication is carried out only with 16 bit (2x1) MUX and shifters. Proposed 16 bit MUX based multiplication is carried out only with 32 bit (2x1) MUX and shifters. The designs’ve been implemented using Verilog and synthesized using Xilinx 13.2 Spartan 3e kit.

Keywords: FIR filter, Look-up Table, Reconfigurable Architecture, and Distributed Arithmetic.