ISSN: 2456-043X

International Journal of Engineering Science and Generic Research

An International Peer Review Journal for Engineering Science and Generic Research

Full Test PDF

FPGA Realization of MUX Based FIR Filter Architecture

K.Sabitha, S.Sreehari

Volume : VOLUME 2 || Issue : ISSUE 5

Abstract :

In digital filter implementation, the multiplier usage is avoided by using MUX based multiplier and Look up Table (LUT) based multiplier. Odd multiple storage proposed by stores the product of odd multiple of co-efficient and the input. The advantage of storing odd multiple is that even multiples can be obtained by a simple left shift operation.MUX based multiplication is carried out only with MUX and shifters and CSLA BEC adder. Proposed MUX based multiplication is carried out only with MUX and shifters and CSLA DLATCH adder. Proposed MUX based CSLA DLATCH adder increases the speed over MUX based CSLA BEC. The designs’ve been implemented using Verilog and synthesized using Xilinx 13.2 Spartan 3e kit.

Keywords: FIR filter, Look-up Table, Reconfigurable Architecture, and Distributed Arithmetic.