ISSN: 2456-043X

International Journal of Engineering Science and Generic Research

An International Peer Review Journal for Engineering Science and Generic Research

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Design and implementation of Floating point multiplication with Karatsuba-Urdhva multiplier and kogge stone adder


Volume : VOLUME 2 || Issue : ISSUE 5

Abstract :

Floating point multiplication is a crucial operation in high power computing applications such as image processing, signal processing etc. And also multiplication is the most time and power consuming operation. This paper proposes an efficient method for IEEE 754 floating point multiplication which gives a better implementation in terms of delay and power. A combination of Karatsuba algorithm and Urdhva-Tiryagbhyam algorithm (Vedic Mathematics) is used to implement unsigned binary multiplier for mantissa multiplication. The multiplier is implemented using Verilog HDL, targeted on Spartan-3E and Virtex-4 FPGA.

Keywords: FPGA, Floating point multiplier, Vedic mathematics, Urdhva-Tiryagbhyam, Karatsuba