ISSN: 2456-043X

International Journal of Engineering Science and Generic Research

An International Peer Review Journal for Engineering Science and Generic Research

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Design of Memory controller with AXI Bus interface


Volume : VOLUME 2 || Issue : ISSUE 5

Abstract :

The on-chip interconnection system known as advanced microcontroller bus architecture (AMBA) is a well-established open specification for the proper management of functional blocks comprising system-on chips (SOCs). An important feature for any of the SoC is based on how they interconnect. The AMBA AXI 4 protocol supports high performance, high-frequency system designs. It is suitable for high-bandwidth and low-latency designs and provides high frequency operation without using complex bridges. In the subject paper, the design and implementation details of AMBA bus (AXI) slave with memory controller (MC) interface are discussed. The AMBA-AXI does not require any bridge like AMBA-AHB. The realization of the control structure is based on the concept of conventional finite state machines (FSMs). The intellectual property (IP) blocks of AXI slave memory controller Designed in verilog and verified on Xilinx Isim simulator.

Keywords: Advanced microcontroller bus architecture (AMBA) Advanced Extensible Interface (AXI), finite-state machines (FSMs), memory controller (MC), system-on-chips (SOCs).