An area-efficient and low-power Multiply Accumulate (MAC) Unit is proposed in this work. The multiplication unit is implemented with vedic multiplier using Urdhava Triyagbhayam Sutra. The Vedic multiplier is used for the multiplication unit so as to reduce partial products and to get high performance and lesser area. The adder unit is implemented using Reversible logic gates. Performance of MAC unit is compared by considering different high performance adders like carry save adder, Kogge-Stone Adder and Brent-Kung Adder for partial product addition in the vedic multiplier. The Vedic Multiplier is designed using Brent Kung Adder that efficiently reduces the area and power consumption compared to other high performance adders. The MAC unit is designed in Verilog HDL; the simulation and synthesis is done in Xilinx 13.2 tool. Keywords: Vedic Multiplier, Urdhava Triyagbhayam, Brent Kung adder, Reversible Logic.