Soft output Viterbi detectors (SOVA) are generally used in all communication receivers within the digital back-end circuitry for explanatory inter symbol interference. Present implementations of the SOVA detector are based on uniform quantization using register exchange logic or with a trace back approach. In this paper, we examine the design architecture and performance examination of a SOVA detector based on non-uniform quantization. The proposed detector was synthesized and place and routed using Xilinx tool chain and implemented on Spartan -3E XC3S1200E-4FG320 field programmable gate array (FPGA) kit. Execution results in FPGA shows that our projected architecture results in decrease in the total number of slice registers decrease in the number of slice look-up table (LUT) and reduction in the delay.
Keywords: SOVA, sliding block, high-throughput, nonuniform quantization.