Floating Point Multiplication is mainly used for high speed operations such as digital image processing and digital signal processing etc. But multiplication is a time taking and power consuming process. In this paper an IEEE754 floating point multiplier is designed and implemented which is efficient in terms of area and delay. For implementing unsigned binary multiplier for mantissa multiplication both Karatsuba and Urdhva- Tiryagbyam which is a sutra of Vedic mathematics is used. The multiplier is implemented using verilog, targeted on Spartan-3E
Keywords: Floating Point Multiplier, Urdhva-Tiryagbyam algorithm and karatsuba algorithm.