ISSN: 2456-043X

International Journal of Engineering Science and Generic Research

An International Peer Review Journal for Engineering Science and Generic Research

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Design of modified Radix-10 parallel multiplier

K.Prasanthi, Mrs.P.AsiyaThapaswin

Volume : VOLUME 3 || Issue : ISSUE 5

Abstract :

The importance of multiplication in various applications necessitates improvement in its design so as to obtain the multiplication result efficiently. Multiplication operation can be improved by reducing the number of partial products to be added and by enhancing the adder unit for obtaining sum. The number of partial products can be reduced by using higher radix multiplication. For better speed applications a radix-10 multiplier is proposed which uses recoded multiplier digits as in conventional parallel multiplier design. The multiplier digits are encoded using Signed Digit (SD) radix-10 method which converts the digit set to {-5 to 5} from {0 to 9} and also generate a sign bit. This recoding leads to minimized calculations as only five multiples are required to be calculated and the negative multiples are obtained using 2's complement approach. The modified architecture eliminates the extra recoding logic thereby reducing the area of overall architecture. This paper delivers the design and implementation of 16-Bit multiplication unit. The design entry is done in Verilog Hardware Description Language (HDL) and simulated using ISIM Simulator. It is synthesized and implemented using Xilinx ISE 14.7.

Keywords: Radix-10 parallel multiplication; Recoded multiplier; BCD multiplier.