ISSN: 2456-043X

International Journal of Engineering Science and Generic Research

An International Peer Review Journal for Engineering Science and Generic Research

Current Issues

Articles:
Solution of Economic Dispatch Problem through Genetic Algorithm

Anuja Priya, Himanshu Sirohia

Volume : VOLUME 1 || Issue : ISSUE 1


Automatic digit recognition and synthesis system for marathi

Professor, Bharti Gawali

Volume : VOLUME 1 || Issue : ISSUE 1


DESIGN AND STRUCTURAL ANALYSIS OF ROTARY CURING MACHINE

Rajasekhar Pusuluri

Volume : VOLUME 1 || Issue : ISSUE 1


REDUCTION OF PEAK POWER AVERAGE RATIO IN OFDM SYSTEM USING CLIPPING TECHNIQUE

Mr.Koushik Chakraborty

Volume : VOLUME 1 || Issue : ISSUE 1




Embedded Based Electronic Voting Machine

Dasari kavitha, Anuja priya

Volume : VOLUME 2 || Issue : ISSUE 1


TOUCH SCREEN BASED INDUSTRIAL LOAD SWITCHING

Shreya sankrityayan, Ananya sankrityayan

Volume : VOLUME 2 || Issue : ISSUE 2


Anti-Theft System

Shreshtha Gupta, Himanshu Sirohia

Volume : VOLUME 2 || Issue : ISSUE 3


16-BIT CARRY SELECT ADDER

Anushree Garg, Himanshu Sirohia

Volume : VOLUME 2 || Issue : ISSUE 3


INTERFACING BETWEEN I2C MASTER AND WISHBONE CONTROLLER

Suman kumawat , Vikram choudhary

Volume : VOLUME 2 || Issue : ISSUE 3


A Review on Comparison on Network on Chip (NOC) Using Simulation Tool NS2

Kusum Kardam, Akanksha Singh

Volume : VOLUME 2 || Issue : ISSUE 3


STUDY OF CUTTING PARAMETERS DURING TURNING OF MMC (STEEL) USING RSM

Sudhanshu Shukla, Abhishek Singh Jatav

Volume : VOLUME 2 || Issue : ISSUE 3


A STUDY OF SURFACE ROUGHNESS IN DRILLING OF AISI H11 USING RSM

Chitranshu Bhawsar and Aditya Sharan Singh

Volume : VOLUME 2 || Issue : ISSUE 3


A review paper on AN EFFECTIVE FULL ADDER DESIGN using different logic style for low power dissipation

Yeshu Mishra, Khushboo Patni

Volume : VOLUME 2 || Issue : ISSUE 3


PROFILE KEYING

Bela Dubey, Aditya Vyas

Volume : VOLUME 2 || Issue : ISSUE 3


Waste Water treatment Management System

Ruchi Kumari, Namrata

Volume : VOLUME 2 || Issue : ISSUE 3


Fpga Implementation of High Performance Fully Pipelined Aes Algorithm Using Reversible Logic

Shilpa B Darvesh1, T. Kavitha2

Volume : VOLUME 2 || Issue : ISSUE 3


DELHI METRO AUTOMATION USING PLC AND SCADA

AKRITI PANDEY

Volume : VOLUME 2 || Issue : ISSUE 3


AUTOMATION OF OIL AND GAS REFINERY PROCESS USING PLC & SCADA

PRIYANKA GUPTA1, PREETI SHAKYAWAR2

Volume : VOLUME 2 || Issue : ISSUE 3


Yield Enhancement Techniques of VLSI Technology

Isha Kashyap1, Jagriti Gupta2

Volume : VOLUME 2 || Issue : ISSUE 3


Design of Four Port Router for Network on Chip Using VERILOG

Ujjwal Kaushik, Shubhangi Jaiswal

Volume : VOLUME 2 || Issue : ISSUE 4


A novel bus Design Technique for On Chip buses to resolve Bus Deadlock

Mohammed Anjum, MD.Mukram Ali,

Volume : VOLUME 2 || Issue : ISSUE 4


Design and implementation of UART with BIST Capability

BAPATLA PRATYUSHA, M.SRINIVASARAO

Volume : VOLUME 2 || Issue : ISSUE 4


Design of 32 bit high speed Six stage Pipeline RISC processor for Convolution

Rudraram Sirisha, Er. Nuli Namassivaya

Volume : VOLUME 2 || Issue : ISSUE 4


A Radiation-Hardened AMBA Bus

Gourav Deep Kaur Bal

Volume : VOLUME 2 || Issue : ISSUE 4


A LOW POWER 32-BIT MAC UNIT DESIGN USING VEDIC MUTIPLIER AND BRENT-KUNG ADDER

Bhavana Paramkusham, T. Kavitha

Volume : VOLUME 2 || Issue : ISSUE 4


FPGA based Performance Analysis of Micro programmed FIR Filters using Multipliers

Pathapati Tanuja, B.Bhavani

Volume : VOLUME 2 || Issue : ISSUE 4


Design and Implementation of Area Efficient S-Box for Fully Pipelined AES

Mrs.Kondisetti Jyothi, Mr.Pattem Sampath Kumar, Mrs.Velaga Rajya Lakshmi,

Volume : VOLUME 2 || Issue : ISSUE 4



RF Front-end Design of a Digital TV Receiver

D.Sony, Dr.G.V. Mahalakshmi

Volume : VOLUME 2 || Issue : ISSUE 5


Design of Area Efficient Substitution-Box with Pipelined AES

K.Keerthi Sucharitha , G. Hamarnath , T.Chakrapani

Volume : VOLUME 2 || Issue : ISSUE 5


DESIGN OF AREA EFFICIENT AND POWER OPTIMIZED CARRY SELECT ADDER

Deepak Kumar, Pathloth Krishnamurthy

Volume : VOLUME 2 || Issue : ISSUE 5


Design of Memory controller with AXI Bus interface

K.KRISHNAIAH, YELGAMONI RAVINDER

Volume : VOLUME 2 || Issue : ISSUE 5


Design of Reconfigurable Architecture for 64-point DCTDesign of Reconfigurable Architecture for 64-point DCT

M.PHANINDRA BABU , MADARAPU AJITHRAO

Volume : VOLUME 2 || Issue : ISSUE 5


FPGA Implementation of Vedic ALU with Application Specific Reversible Gates

Marri Vasudha , V.Suresh Kumar

Volume : VOLUME 2 || Issue : ISSUE 5


Design and Implementation of radix Booth Multiplier with BIST TPG

K.Rajani , Prof.I.Venugopal

Volume : VOLUME 2 || Issue : ISSUE 5


Design of 64-Bit Vedic Multiplier and Square Architectures

Kriti Rashmi Sinha , Pathloth Krishnamurthy

Volume : VOLUME 2 || Issue : ISSUE 5


DESIGN OF EFFICIENT RECONFIGURABLE INTERPOLATION FILTER

V. Rajendra chary, C. Pamuleti

Volume : VOLUME 2 || Issue : ISSUE 5


Design and Implementation of Sequential and Parallel FIR Filters using Vedic Multiplier with Compressors

APPAM TEJASWI , MADARAPU AJITHRAO

Volume : VOLUME 2 || Issue : ISSUE 5



DESIGN OF 64 bit MAC UNIT WITH VEDIC MULTIPLIER AND REVERSIBLE DKG GATE

K.RAVI, MADARAPU AJITHRAO

Volume : VOLUME 2 || Issue : ISSUE 5


FPGA Realization of MUX Based FIR Filter Architecture

K.Sabitha, S.Sreehari

Volume : VOLUME 2 || Issue : ISSUE 5


Design of radix 2 and radix4 multipliers with BIST

A.SREENU NAIK, YELGAMONI RAVINDER

Volume : VOLUME 2 || Issue : ISSUE 5


Design and Implementation of Convolution and Deconvolution by using Sutras

Allakonda VamshiKrishna, A Karthik, Dr K Srinivasulu

Volume : VOLUME 2 || Issue : ISSUE 5


Design and Implementation of Area Efficient S-Box using Combinational logic with Pipelined AES

G.Hymavathi , V.Venkanna

Volume : VOLUME 2 || Issue : ISSUE 5


FPGA Implementation of 16 bit MUX Based Multiplier

Jaganmohan, K.Rambabu

Volume : VOLUME 2 || Issue : ISSUE 5


DESIGN AND IMPLEMENTATION OF RECONFIGURABLE 64-POINT DISCRETE COSINE TRANSFORM (DCT) ARCHITECTURE

Meesala Shiva Kumar, Dr. G V Maha Lakshmi

Volume : VOLUME 2 || Issue : ISSUE 5


Design of SPI Bus Protocol with Built-In-Self-Test using CA

GANTI PRAVEEN ANAND 1, N.LATHA

Volume : VOLUME 2 || Issue : ISSUE 5


CRYPTOGRAPHIC TECHNIQUE BY SQUARE MATRIX AND SINGLE POINT CROSSOVER ON BINARY FIELD

MR. G. RAVI KISHORE, MS. SABA NAUSHEEN

Volume : VOLUME 2 || Issue : ISSUE 6


Design of floating point multiplier using karatsuba - urdhava multiplier and koggestone adder

U.Sudharani, K.Siva Sundari

Volume : VOLUME 2 || Issue : ISSUE 5


Quad-Fault Tolerant Architecture Design for Ripple Carry Adder

Vayalasetti Swarnalatha, Praveen Kumar Polisetty

Volume : VOLUME 2 || Issue : ISSUE 5


Implementation of SHA-2(256) & SHA-3(512) Algorithms for Information Security

M.Mounika , T.Thammi Reddy

Volume : VOLUME 2 || Issue : ISSUE 5


DESIGN AND IMPLEMENTATION OF SEQUENTIAL AND PARALLEL MICROPROGRAMMED FIR FILTER

S.Sravanthi, K.Naga Koushil Reddy

Volume : VOLUME 2 || Issue : ISSUE 5


Design and Implementation of MUX Based FIR filter with Hybrid Adder

U.PRAVEEN KUMAR, W.YASMEEN

Volume : VOLUME 2 || Issue : ISSUE 5


EFFICIENT SCALABLE FIR FILTER IMPLEMENTATION USING VEDIC MULTIPLIERS

Chunduri Krishna Chaitanya, K V S Sri Harsha

Volume : VOLUME 2 || Issue : ISSUE 5




Design of Fully Pipelined 128-bit AES with S-Box by using Combinational Logic

SHAIK VAZID AHAMMED, JAI KUMAR VINAYAGAM

Volume : VOLUME 2 || Issue : ISSUE 6


Design and Implementation of Scalable and Reconfigurable Approximation of DCT

B. HYMAVATHI, Dr. S. BALAJI, D. ANJANEYULU

Volume : VOLUME 3 || Issue : ISSUE 1


Design and Implementation of FIR Interpolation Filter with Pipelining

V JAGAN MOHAN, Dr. S. BALAJI, MUNI PRAVEENA RELA

Volume : VOLUME 3 || Issue : ISSUE 1


DESIGN OF FIR FILTER USING VEDIC MULTIPLIER WITH COMPRESSORS AND PROPOSED CSLA

G.Divya, V.Malleswara Rao

Volume : VOLUME 3 || Issue : ISSUE 1


To conduct of various Curing Methods of impression on the Compressive Strength of cement Concrete

Dr.Sanjeev Gill 1 Dr.Rajeev kumar 2

Volume : VOLUME 3 || Issue : ISSUE 2


Role of Nanotechnology in civil construction material as Concrete

Dr.Sanjeev Gill1, Siddhant Bansal2

Volume : VOLUME 3 || Issue : ISSUE 2


A Review on Rural Electrification

BANOTHU MOHAN

Volume : VOLUME 3 || Issue : ISSUE 2


Low Cost Electrification by Using Solar Energy

BANOTHU MOHAN

Volume : VOLUME 3 || Issue : ISSUE 2


A Practical Study, Analysis & Implementation of Hybrid Power Plant Comprising Solar and Wind

Vijay Singh1, Sadaf Siddiqui2, Rajkumar Kaushik3

Volume : VOLUME 3 || Issue : ISSUE 3



Wireless Gesture Controlled Robot

Huma khan

Volume : VOLUME 3 || Issue : ISSUE 3


Advance SMS Based Voting System

Priya Singh

Volume : VOLUME 3 || Issue : ISSUE 3


Low Delay based Quaternary Signed Digit number Addition

Anushree Garg

Volume : VOLUME 3 || Issue : ISSUE 3


Optical Fiber Communication

Pooja Sarav

Volume : VOLUME 3 || Issue : ISSUE 3


Layout Design & Power Scaling Technique in 3D Integrated Circuits

Uma Maheshwari

Volume : VOLUME 3 || Issue : ISSUE 3


Laser Torch Based Voice Transmitter and Receiver

Amreen Niyazi

Volume : VOLUME 3 || Issue : ISSUE 3


Rear View Automatic Car Parking System

Damini Kundal

Volume : VOLUME 3 || Issue : ISSUE 3


Voice Recognition System Through MATLAB

Juhi Khichi

Volume : VOLUME 3 || Issue : ISSUE 3


GSM BASED VOTING MACHINE SYSTEM

Nupur Gupta

Volume : VOLUME 3 || Issue : ISSUE 3


Vehicle Recognition System

Lavina Khichi

Volume : VOLUME 3 || Issue : ISSUE 3


Speed Control Car by DC Motor Using School Area (PWM)

Jyoti Chandra

Volume : VOLUME 3 || Issue : ISSUE 3


Adaptive Technology PIR Based Raw and IB Security System

Anjali Priya

Volume : VOLUME 3 || Issue : ISSUE 3


Automatic Accident Detection and Notification System

Beauty Kumari

Volume : VOLUME 3 || Issue : ISSUE 3


GSM Based Voting Machine Using SMS

Sakshi Mishra

Volume : VOLUME 3 || Issue : ISSUE 3


Implementation of Traffic Light Controller Using VHDL

Parul Aggrawal

Volume : VOLUME 3 || Issue : ISSUE 3


Online Mobile Shopping

Rashmi Sreyash

Volume : VOLUME 3 || Issue : ISSUE 3


FINGERPRINT BASED ATTENDANCE SYSTEM

chetna Anand

Volume : VOLUME 3 || Issue : ISSUE 3


Design and implementation of Wallace tree multiplier using parllel prefix adder (Kogge Stone adder)

Telagathoti Koteswara Rao, Prakash Palachuru

Volume : VOLUME 3 || Issue : ISSUE 4


Optimized BIST Based Radix-4 Booth Multiplier Using FPGAs

Mittapally Kranthi Kiran, M.Renuka

Volume : VOLUME 3 || Issue : ISSUE 4


Design of High Secure Authentication using SHA3-1024 Algorithm for Digital Signatures

Naga Sindhu Somasi, Saidulu Inamanamelluri

Volume : VOLUME 3 || Issue : ISSUE 4


Design of Fault Tolerant Parallel FFTs using Parity SOS Scheme

GUDDETI SRAVANI, D.GHOUSE KARIM

Volume : VOLUME 3 || Issue : ISSUE 5


Design of modified Radix-10 parallel multiplier

K.Prasanthi, Mrs.P.AsiyaThapaswin

Volume : VOLUME 3 || Issue : ISSUE 5


Design of High-Performance Montgomery Modular Multiplication

DIBBAGANDLA SURENDRA, G.JAGADEESWAR REDDY

Volume : VOLUME 3 || Issue : ISSUE 5


Design of Optimized Radix-2 and Radix-4 Butterflies from FFT with Decimation in Time

K. MARYANGELEENA KONKARI, V. RAMESH

Volume : VOLUME 3 || Issue : ISSUE 5


Effective Implementation of Dual Key Based AES Encryption with Key Based S-Box Generation

Manohar Nagallapati, K. Naveen Kumar Raju

Volume : VOLUME 3 || Issue : ISSUE 5



Design and Implementation of a Pipelined 64 bit MAC Unit with Vedic Multiplier and Reversible DKG Gate

Akula Alivelu, Sandeep Chilumula

Volume : VOLUME 3 || Issue : ISSUE 5


Design and Implementation of 64-Bit Vedic Multiplier and Square Architectures

CH.Roja, K. Chinna Akkaiah

Volume : VOLUME 3 || Issue : ISSUE 5


Symmetric transparent BIST for memory using March X algorithm

G Dhanalakshmi, SK SIRAJ

Volume : VOLUME 3 || Issue : ISSUE 5


Design of High Performance and Efficient Blowfish Algorithm by using 512 ROM Based S-Box

Mummadi Rajeswari, Sandeep Chilumula

Volume : VOLUME 3 || Issue : ISSUE 5


Design and Implementation of Pipelined SEC-DEAC (72,64) Codes

Yogesh Eppa , Ganji Annapurna

Volume : VOLUME 3 || Issue : ISSUE 5


Design and Implementation of Reconfigurable Architecture for 64-Point Discreet Cosine Transform

Sudidela Hanumanthareddy, Shaik Rahamtula

Volume : VOLUME 3 || Issue : ISSUE 5


A Novel VLSI Architecture for Convolution using 32 bit Higher Radix Algorithm

Akula Saritha, K.Tarangini

Volume : VOLUME 3 || Issue : ISSUE 5


AN EFFICIENT AND HIGH PERFORMANCE SOVA DETECTOR ON FPGA

Gundaram Priyanka , G.Ravi Kumar

Volume : VOLUME 3 || Issue : ISSUE 5





Design of 128 bit Q-format multiplier by using Higher Radix Algorithm

K.Mounika 1, A. Jaya Lakshmi

Volume : VOLUME 3 || Issue : ISSUE 6


An Efficient Linear Convolution using Higher Radix Booth encoding, Algorithm

Mudragada Siva Ramakrishna, Shilpa Samarla, Seelam Srinivas Rao

Volume : VOLUME 3 || Issue : ISSUE 6


Design of High Performance Blowfish Algorithm by using 512 ROM Based S-Box

P. GANGYA NAIK, EASARI PARUSHA RAMU, K. ASHOK BABU

Volume : VOLUME 3 || Issue : ISSUE 6