ISSN: 2456-043X

International Journal of Engineering Science and Generic Research

An International Peer Review Journal for Engineering Science and Generic Research

Archive

Articles:
RF Front-end Design of a Digital TV Receiver

D.Sony, Dr.G.V. Mahalakshmi

Volume : VOLUME 2 || Issue : ISSUE 5


Design of Area Efficient Substitution-Box with Pipelined AES

K.Keerthi Sucharitha , G. Hamarnath , T.Chakrapani

Volume : VOLUME 2 || Issue : ISSUE 5


DESIGN OF AREA EFFICIENT AND POWER OPTIMIZED CARRY SELECT ADDER

Deepak Kumar, Pathloth Krishnamurthy

Volume : VOLUME 2 || Issue : ISSUE 5


Design of Memory controller with AXI Bus interface

K.KRISHNAIAH, YELGAMONI RAVINDER

Volume : VOLUME 2 || Issue : ISSUE 5


Design of Reconfigurable Architecture for 64-point DCTDesign of Reconfigurable Architecture for 64-point DCT

M.PHANINDRA BABU , MADARAPU AJITHRAO

Volume : VOLUME 2 || Issue : ISSUE 5


FPGA Implementation of Vedic ALU with Application Specific Reversible Gates

Marri Vasudha , V.Suresh Kumar

Volume : VOLUME 2 || Issue : ISSUE 5


Design and Implementation of radix Booth Multiplier with BIST TPG

K.Rajani , Prof.I.Venugopal

Volume : VOLUME 2 || Issue : ISSUE 5


Design of 64-Bit Vedic Multiplier and Square Architectures

Kriti Rashmi Sinha , Pathloth Krishnamurthy

Volume : VOLUME 2 || Issue : ISSUE 5


DESIGN OF EFFICIENT RECONFIGURABLE INTERPOLATION FILTER

V. Rajendra chary, C. Pamuleti

Volume : VOLUME 2 || Issue : ISSUE 5


Design and Implementation of Sequential and Parallel FIR Filters using Vedic Multiplier with Compressors

APPAM TEJASWI , MADARAPU AJITHRAO

Volume : VOLUME 2 || Issue : ISSUE 5



DESIGN OF 64 bit MAC UNIT WITH VEDIC MULTIPLIER AND REVERSIBLE DKG GATE

K.RAVI, MADARAPU AJITHRAO

Volume : VOLUME 2 || Issue : ISSUE 5


FPGA Realization of MUX Based FIR Filter Architecture

K.Sabitha, S.Sreehari

Volume : VOLUME 2 || Issue : ISSUE 5


Design of radix 2 and radix4 multipliers with BIST

A.SREENU NAIK, YELGAMONI RAVINDER

Volume : VOLUME 2 || Issue : ISSUE 5


Design and Implementation of Convolution and Deconvolution by using Sutras

Allakonda VamshiKrishna, A Karthik, Dr K Srinivasulu

Volume : VOLUME 2 || Issue : ISSUE 5


Design and Implementation of Area Efficient S-Box using Combinational logic with Pipelined AES

G.Hymavathi , V.Venkanna

Volume : VOLUME 2 || Issue : ISSUE 5


FPGA Implementation of 16 bit MUX Based Multiplier

Jaganmohan, K.Rambabu

Volume : VOLUME 2 || Issue : ISSUE 5


DESIGN AND IMPLEMENTATION OF RECONFIGURABLE 64-POINT DISCRETE COSINE TRANSFORM (DCT) ARCHITECTURE

Meesala Shiva Kumar, Dr. G V Maha Lakshmi

Volume : VOLUME 2 || Issue : ISSUE 5


Design of SPI Bus Protocol with Built-In-Self-Test using CA

GANTI PRAVEEN ANAND 1, N.LATHA

Volume : VOLUME 2 || Issue : ISSUE 5


Design of floating point multiplier using karatsuba - urdhava multiplier and koggestone adder

U.Sudharani, K.Siva Sundari

Volume : VOLUME 2 || Issue : ISSUE 5


Quad-Fault Tolerant Architecture Design for Ripple Carry Adder

Vayalasetti Swarnalatha, Praveen Kumar Polisetty

Volume : VOLUME 2 || Issue : ISSUE 5


Implementation of SHA-2(256) & SHA-3(512) Algorithms for Information Security

M.Mounika , T.Thammi Reddy

Volume : VOLUME 2 || Issue : ISSUE 5


DESIGN AND IMPLEMENTATION OF SEQUENTIAL AND PARALLEL MICROPROGRAMMED FIR FILTER

S.Sravanthi, K.Naga Koushil Reddy

Volume : VOLUME 2 || Issue : ISSUE 5


Design and Implementation of MUX Based FIR filter with Hybrid Adder

U.PRAVEEN KUMAR, W.YASMEEN

Volume : VOLUME 2 || Issue : ISSUE 5


EFFICIENT SCALABLE FIR FILTER IMPLEMENTATION USING VEDIC MULTIPLIERS

Chunduri Krishna Chaitanya, K V S Sri Harsha

Volume : VOLUME 2 || Issue : ISSUE 5